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OZ813
Ultra High Efficiency Dual DC-DC Controller
FEATURES
* * * * * * * * * * * * * * * * Dual DC-DC SMPS controller with integrated drivers Two constant ripple-current controllers Constant ripple-current control allows optimum inductor size High full load efficiency; up to 94% High light load efficiency; >85% at 100mA Vout accuracy; 1% or better Input voltage; from 3V to 26V Output voltage - adj. from 0.5V to 2.75V Output current - up to 15A Independent o Power Good signals o ON/SKIP signals Soft-Start at start-up Soft-stop at shutdown Voltage Feed-Forward Compensation User adjustable operating frequency Dynamic voltage change support Output Protection: o Latched Over Voltage Protection o Latched Under Voltage Protection o Valley type Over Current Protection Input Protection: o Under Voltage Lock Out on VDDA o Under Voltage Lock Out on VIN
GENERAL DESCRIPTION
OZ813 is a DC/DC controller specially developed to design power supplies for next generation microprocessors, their peripherals and chipsets. OZ813 steps down the high battery voltage to low output voltages in the range of 0.5V to 2.75V. High efficiency, DC accuracy and excellent transient response make OZ813 suitable for supplying low voltage CPU peripherals, chipset cores, and graphics processors. OZ813 has two independent constant ripple-current buck controllers with powerful integrated drivers able to drive output currents up to 15A. Voltage Feed-Forward compensation assures high rejection of input voltage transients typically occurring when the AC adapter is plugged in or removed. Over Voltage Protection (OVP) acts when the output voltage exceeds the set voltage by more than 125mV. This protection condition is latched and initiates a ramp down of the output voltage. Under Voltage Protection (UVP) acts when the output voltage falls below the set voltage by more than 133mV. This protection condition is latched and initiates a ramp down of the output voltage. After an OVP or UVP event, the ON/SKIP pin should be toggled or VDDA/VIN cycled to restart the circuit. Both outputs are protected against overload by individual, valley current type, cycle-by-cycle (Over Current Protection) OCP circuits. The Under Voltage Lock Out circuit monitors both, VDDA and VIN and lets the controller operate only if VDDA > 4.3V and VIN > 2.5V. The Power Good signal is high as long as the output voltage is within +125mV/-133mV of the set voltage. At startup the output voltage ramps up in a controlled manner with a typical slew rate of 1V/ms and at shutdown the output voltage is ramped down in a controlled manner with the same slew rate.
*
APPLICATIONS
Power Supplies for Notebook CPU and Peripherals
ORDERING INFORMATION
Part Number OZ813LN Temp Range o o 0 C to 85 C Package QFN24 Lead-Free
SIMPLIFIED APPLICATION DIAGRAM
PIN DIAGRAM
VSET2 HDR2 HDR1 PGD2 PGD1 CS2N CS2P LX2 LX1
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VSET1 CS1N CS1P
07/31/08 OZ813-SF-v1.3 Copyright (c) 2004-2008 by O2Micro All Rights Reserved Patents #6,965,221; 7,202,650; 6,844,710; 7,098,642 and others pending
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OZ813
PIN DESCRIPTION
No. Name I/O Type Description Enables Channel 2 operation. If VON/SKIP2 > 0.6V, the Vout2 voltage ramps up to the voltage set on VSET2 pin with a slew rate of 1V/ms. If VON/SKIP2 > 2.1V the controller enters skip mode of operation. If both ON/SKIP1 and ON/SKIP2 pins are < 0.4V the chip is disabled and enters a very low consumption mode < 1A. To re-enable the controller the voltage on at least one of the ON/SKIP pins need to exceed 1V. Once the chip is enabled the conditions above applies. Input voltage sense. Used for feed-forward compensation. Also monitored by the Under Voltage Lock Out circuit. Let the controller operate only if Vin > 2.5V. Must be connected to the input voltage of the power stage. 2.75V +/- 1% precision reference voltage. A 0.1F should be placed from VREF to GNDA. Adjust the Ton of the controller according to the formula: Ton = (1.6s*VTSET)/(Vin-Vout) A 0.1F capacitor must be placed from TSET to GNDA. +5V supply for the controller analog circuits. A 1F capacitor should be placed from VDDA to GNDA. Enables Channel 1 operation. If VON/SKIP1 > 0.6V, the Vout1 voltage ramps up to the voltage set on VSET1 pin with a slew rate of 1V/ms. If VON/SKIP1 > 2.1V the controller enters skip mode of operation. If both ON/SKIP1 and ON/SKIP2 pins are < 0.4V the chip is disabled and enters a very low consumption mode < 1A. To re-enable the controller the voltage on at least one of the ON/SKIP pins need to exceed 1V. Once the chip is enabled the conditions above applies. Sets the Vout1 output voltage of the first controller. Uses a resistor divider from the reference voltage. Inverting current sense pin for channel 1. Non-inverting current sense pin for channel 1. Power Good output for Vout1. It is an open drain output asserted high when the output voltage Vout1 is within +125mV/-133mV of the set value. Inductor switching node for channel 1. Output of the high side driver for channel 1. Positive supply for the high side driver of channel 1. A 0.1F capacitor should be placed between BST1 and LX1. Output of the low side driver for channel 1. Power Ground. Positive supply for the low side driver. A 1F capacitor should be placed from VDDP to GNDP. Output of the low side driver for channel 2. Positive supply for the high side driver of channel 2. A 0.1F capacitor should be placed between BST2 and LX2. Output of the high side driver for channel 2. Inductor switching node for channel 2. Power Good output for Channel2. It is an open drain output asserted high when output voltage Vout2 is within +125mV/-133mV of the set value. Non-inverting current sense pin for channel 2. Inverting current sense pin for channel 2. Sets the Vout2 output voltage of the second controller. Uses a resistor divider from the reference voltage. Ground for the controller analog circuits.
1
ON/SKIP2
I
Digital
2 3 4 5
VIN VREF TSET VDDA
I O P P
Analog Analog Power Power
6
ON/SKIP1
I
Digital
7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSET1 CS1N CS1P PGD1 LX1 HDR1 BST1 LDR1 GNDP VDDP LDR2 BST2 HDR2 LX2
I I I O P O P O P P O P O P O I I I P
Analog Analog Analog Digital Power Digital Power Digital Power Power Digital Power Digital Power Digital Analog Analog Analog Power
21 PGD2 www..com 22 23 24 25 CS2P CS2N VSET2 GNDA
OZ813-SF-v1.3
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TYPICAL APPLICATION SCHEMATIC
+3V3 +VDC +5V R21 1k9 PGD2 CIN2 10uF_25V CS2N CS2P LX2 HDR2 M2 R02 22 C21 0.1uF LDR2 BST2 1 2 3 4 S1 G1 S2 G2 Si4830DY +VDC CS2P BST2 LDR2 VDDP GNDP LDR1 BST1 18 17 16 15 14 13 D2 MBR0540 +5V D1 MBR0540 C03 1uF BST1 LDR1 C11 0.1uF C04 R04 1nF 20k CS1P +3V3 VSET2 CS1N C13 C05 150k 1k9 1nF 0 PGD1 R01 22pF 1nF C14 HDR1 LX1 CS1P CS1N 1 2 3 4 M1 S1 G1 S2 G2 Si4830DY R12 100k R13 C12 60k 3.3nF D1 D1 D2 D2 8 7 6 5 L1 3.3uH/5A 28mohm R14 51 COUT1 2x100uF_6V CIN1 10uF_25V CS2N C23 22pF C24 1nF C22 3.3nF D1 D1 D2 D2 8 7 6 5 R24 51 R22 100k R23 60k COUT2 2x100uF_6V L2 3.3uH/5A 28mohm +VDC
25
U1
GNDA
ON/SKIP2 VREF VDDA ON/SKIP1 C01 C02 0.1uF R03 105k VSET1 1uF
1 2 3 4 5 6
ON/SKIP2 VIN VREF TSET VDDA ON/SKIP1
VSET2 CS2N CS2P PGD2 LX2 HDR2
24 23 22 21 20 19
7 8 9 10 11 12
VSET1 CS1N CS1P PGD1 LX1 HDR1
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OZ813
1.5V/5A
VSET2
OZ813 QFN24
1.7V/5A
Single point ground connection
R05 R11
Signal Ground
Power Ground
Figure 16. Typical Chipset Power Supply Schematic
OZ813-SF-v1.3
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OZ813
BILL OF MATERIALS
Item 1 Qty 2 Reference CIN1, CIN2 Value 10u/25V Vendor Taiyo-Yuden Johanson Dielectrics TDK Taiyo-Yuden Johanson Dielectrics TDK Any Taiyo-Yuden Johanson Dielectrics TDK Any Any Any Any Any Any Any Any Any Any Any Any Vishay Vishay Fairchild Vishay TOKO O2Micro, Inc. Part Number TMK325BJ106MM-B 250S41X106M C3225X7R1E106M JMK325BJ107MY-T 6R3S41X107M C3225X5R0J107M Ceramic - X7R or X5R EMK107BJ105KA-B 100R14X105M C1608X5R1A105K Ceramic - X7R or X5R Ceramic - X7R or X5R Ceramic 1210 PCB Footprint
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
2 3 2 2 4 2 1 1 1 1 1 2 2 2 2 2 2 2 1
COUT1, COUT2 C02, C11, C21 C01, C03 C12, C22 C04, C05, C14, C24 C13, C23 R01 R02 R03 R04 R05 R11, R21 R12, R22 R13, R23 R14, R24 D1, D2 M1, M2 L1, L2 U1
2x100uF/6V 0.1uF/10V 1uF/10V 3.3nF/25V 1nF/6V 22pF 0 22 105k 1% 20k 1% 150k 1% 1k9 100k 1% 60k 1% 51 NONE NONE 3.3u/5A OZ813
1210 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SOD-123 SO-8 2525 QFN24
MBR0540 Si4830DY FDS6982S IHLP2525CZ-01 FDV0630 3R3 OZ813
COMPONENT SUPPLIERS
Manufacturer Power MOSFETs Vishay Fairchild Inductors Vishay TOKO Diode Vishay Fairchild Capacitors Taiyo-Yuden Johanson Dielectrics TDK Resistors www..com Vishay TDK Contact Information Phone 1-402-563-6866 1-703-478-5800 1-402-563-6866 1-408-432-8281 1-402-563-6866 1-703-478-5800 Website www.vishay.com www.fairchildsemi.com www.vishay.com www.toko.com www.vishay.com www.fairchildsemi.com www.t-yuden.com www.johansondielectrics.com www.tdk.com www.vishay.com www.tdk.com
1-818-364-9800 1-800-344-2112 1-402-563-6866 1-800-344-2112
OZ813-SF-v1.3
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OZ813
PACKAGE INFORMATION
Exposed pad at bottom is GNDA (pin 25) and must be fully soldered to PCB
PIN 1 ID
1 2 3
PIN 1 ID
1 2 3
TOP VIEW
BOTTOM VIEW
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Rth j-a (QFN-24 4x4mm package) = 38C/W Rth j-c (QFN-24 4x4mm package) = 4.8C/W
OZ813-SF-v1.3
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OZ813
DIMENSION TABLE
SYMBOL Pitch 0.50 SPECIFICATION Nom Max 0.90 4.00 4.00 0.18 .25 .30 .50 0.30 0.40 0.50 2.80 0.25 0.50 0.80 2.50 3.20 Min
A B C D E L P D1 E1 L1 P1 F
Notes: 1. Controlling dimensions are in millimeters (mm). 2. Pin #1 count orientation shall be in a counterclockwise direction as viewed in live-bug position.
LANDING PATTERN
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OZ813-SF-v1.3
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OZ813
PACKAGE MARKING (QFN24 PACKAGE) 813L _
Mark
Function
Lead-Free Package
N
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OZ813-SF-v1.3
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OZ813
IMPORTANT NOTICE
No portion of O2Micro specifications/datasheets or any of its subparts may be reproduced in any form, or by any means, without prior written permission from O2Micro. O2Micro and its subsidiaries reserve the right to make changes to their datasheets and/or products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. O2Micro warrants performance of its products to the specifications applicable at the time of sale in accordance with O2Micro's standard warranty. Testing and other quality control techniques are utilized to the extent O2Micro deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customer acknowledges that O2Micro products are not designed, manufactured or intended for incorporation into any systems or products intended for use in connection with life support or other hazardous activities or environments in which the failure of the O2Micro products could lead to death, bodily injury, or property or environmental damage ("High Risk Activities"). O2Micro hereby disclaims all warranties, and O2Micro will have no liability to Customer or any third party, relating to the use of O2Micro products in connection with any High Risk Activities. Any support, assistance, recommendation or information (collectively, "Support") that O2Micro may provide to you (including, without limitation, regarding the design, development or debugging of your circuit board or other application) is provided "AS IS." O2Micro does not make, and hereby disclaims, any warranties regarding any such Support, including, without limitation, any warranties of merchantability or fitness for a particular purpose, and any warranty that such Support will be accurate or error free or that your circuit board or other application will be operational or functional. O2Micro will have no liability to you under any legal theory in connection with your use of or reliance on such support. COPYRIGHT (c) 2004-2008, O2Micro International Limited
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OZ813-SF-v1.3
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